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Technical Paper

Managing the balance between performance optimization and debuggability in LVS circuit verification

Screenshot of equivalent hcell lists in layout and source netlists
The ongoing need for both accuracy and speed in circuit verification gives rise to a conflict between LVS performance optimization and debuggability. Balancing the trade-offs between performance and debuggability is a crucial step towards achieving a robust and efficient circuit verification process. One option that considers both the design hierarchy and the current “cleanliness” of a design is to run hierarchical LVS with a carefully defined set of hcells to provide as much debugging support as possible without severely impacting extraction and comparison runtime performance. Early identification of this sweet spot is crucial, especially when the designs are dirty and maximum debuggability is crucial to enable layout engineers to easily identify sources of design violations.

The Calibre nmLVS tool supports hierarchical LVS for faster runtimes and improved debuggability of IC design layouts

To help design teams balance performance optimization and debuggability in LVS physical circuit verification, the Calibre nmLVS and Calibre Interactive tools provide automated cell placement expansion, including the automatic generation of different hcell lists that cover different ranges of hierarchy depths. This expansion helps optimize the IC design hierarchy for both performance and debuggability. Designers and CAD engineers can coordinate (based on the design hierarchy and its degree of cleanliness) to define the level of hcells that are kept in these hcell lists. Using different options for hcells for different runs offers designers more debuggability options by using a bigger hcell list in very early phases when designs are dirty, and enable designers to achieve faster performance turnaround time later on, by using a small set of hcells when designs are cleaner.

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