Improving yield for new design styles during technology development

Predicting and improving wafer yield in the early stages of technology development is a primary reason for creating test macros on test masks. Identifying potential yield failures in the early technology development phase enables design teams to implement upstream corrective actions and/or process changes that reduce the time it takes to achieve the desired manufacturing yield in production. However, it can be difficult to design accurate test structures for new design styles and technologies that have no relevant history.

Improving wafer yield for new IC design styles during technology node development

The innovative layout schema generator (LSG) process enables design teams to generate additional macros to add to test structures without relying on past designs for input. LSG macros are based on the generation and random placement of unit patterns that can construct more meaningful larger patterns. By using the LSG process, designers can significantly reduce the time it takes to achieve the desired wafer yield for designs that include new design techniques.