How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability

In the fast-paced world of semiconductor design, achieving both Design Rule Check (DRC) clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. This paper explores how the Calibre DesignEnhancer (DE) analysis-based, signoff-quality EMIR solution helps design teams meet these challenges by enhancing power integrity and reducing IR drop. Calibre DE improves design reliability and manufacturability across multiple foundry technologies, reduces support costs and increases usability for foundries, CAD teams, and designers.

This paper demonstrates that by leveraging the power of Calibre DE, companies like Intel and Google can streamline their design processes, enhance power integrity, and ultimately achieve superior IC designs, faster and with greater reliability.

What you’ll learn:

• How Calibre DesignEnhancer's deep understanding of design rules enables maximizing via insertion while maintaining DRC compliance, leading to improved power delivery and reduced IR drop.
• Examples of how Intel and Google used Calibre DesignEnhancer to enhance their design flows, boost power integrity, and achieve superior IC designs faster.
• The importance of a flexible, foundry-independent solution that integrates seamlessly into existing design environments to streamline the layout optimization process.
• How Calibre DesignEnhancer's correct-by-construction approach ensures layout modifications improve both design performance and time-to-market without sacrificing DRC compliance.

Who should read this:

• IC designers
• CAD engineers and engineering managers
• Power integrity and reliability engineers