Full-chip electrical reliability verification: A new approach for advanced process nodes

Advanced nodes introduce new and complex reliability conditions that can’t be easily or accurately checked using dynamic simulation or traditional physical and circuit verification technology at the full-chip level. Advanced reliability verification techniques and tools employ static simulation and static voltage propagation in conjunction with logic-driven layout analysis to provide accurate, fast, automated reliability design verification for complex issues like electrostatic discharge, latch-up, and time-dependent dielectric breakdown. Designers can now verify that their IC designs are protected against a wide range of reliability issues, ensuring that the final product provides the performance and product life the market demands.

Resolve complex IC design reliability issues like electrostatic discharge, latch-up, and time-dependent dielectric breakdown with fast, accurate, automated IC reliability verification

The Calibre® PERC™ reliability platform is specifically designed to perform a wide range of complex reliability verification tasks using both standard rules from the foundry and custom rules created by a design team. Using Calibre PERC static simulation and static voltage propagation in conjunction with the Calibre PERC logic-driven layout flow, foundries/IDMs can now clearly define ESD and LUP rules with assurance of 100% coverage based on their rule requirements, and design companies can easily implement automated full-chip ESD, LUP and TDDB rule checking.