EUV full-chip curvilinear mask options for logic via and metal patterning

Generating EUV full chip curvilinear masks offers maximum process window but the technology used to produce these masks remains too slow for full-chip logic manufacturing. We review several alternative approaches to using only inverse lithography technology (ILT) that offer between 4x to over 100x faster runtime with very similar lithographic metrics.

What you'll learn:

• Why inverse lithography technology (ILT) is not practical for EUV full-chip curvilinear mask generation.
• What alternative approaches exist with faster runtime that also achieve maximum process window.
• How to produce curvilinear output masks with between 4x and over 100x faster runtime.

Who should read this:

• Mask data preparation engineers
• Lithography process engineers
• IC manufacturing and process integration engineers
• R&D scientists in semiconductor fabrication