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Technical Paper

Enhancing guard ring verification for latch-up prevention at advanced nodes

Screenshot of an IC device layout surrounded by a guard ring
Physical verification of guard ring structures is critical to reducing potential latch-up scenarios in advanced process technology layouts. This verification includes determining path resistance of the guard rings, identifying the bias of the guard rings used in multiple voltage domains, verifying the exclusivity of the aggressor devices within the ring, and identifying areas of weakness as a result of too few vias and contacts, or the presence of narrow interconnects. The Calibre® PERC™ reliability platform provides automated guard ring analysis that includes guard ring detection, resistance and voltage bias calculations, and physical layout analysis. By enhancing and automating guard ring verification, the Calibre PERC platform enables design teams to ensure effective protection against latch-up in the most complex and advanced node integrated circuit (IC) designs.

Guard ring verification at advanced process nodes

Verifying the existence and accurate construction of guard rings around aggressors and between potential victims using electronic design automation (EDA) tools is a standard physical verification process. However, at advanced process technology nodes, smaller geometries with higher density per unit area, more narrow and resistive interconnect, and the use of multiple power domains make latch-up prevention and guard ring verification more challenging than ever.

The Calibre PERC reliability platform can automatically identify intentional layout devices with diffusion regions, as well as biased guard ring structures placed around potential injector devices typically connected to I/O pads, using circuit topology tracing to identify specific nets or devices that represent paths to the pads, so these paths can be evaluated for the presence of guard rings. The Calibre PERC platform can then perform a variety of point to point (P2P) and path resistance measurements for each guard ring, automatically adding voltage information to the path for detailed analysis. It also uses a static solver to produce current density data for evaluating the guard ring resistance by layer. Together, these capabilities enable design teams to confirm their guard ring structures provide the intended protection against latch-up.

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