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Technical Paper

Efficient and accurate parasitic extraction for leading-edge process node IC designs

Diagrams of a finFET and a gaafet transistor
Designing integrated circuits (ICs) for the latest process nodes always reveals new impacts and influences on layouts. Parasitic extraction (PEX) ensures design teams can accurately identify and account for all parasitics when evaluating circuit performance and reliability. With each new process node, the distance between IC components shrinks. With more densely packed devices and interconnects in advanced nodes, parasitics become more pronounced, and error margins shrink. New architectures introduce new parasitics impacts. The comprehensive circuit analysis and parasitic calculation capabilities of the Calibre parasitic extraction tools enable designers to perform accurate and efficient modeling of advanced node design parasitics. Customizable techniques help design teams effectively manage parasitics while ensuring optimal design performance.

Calibre extraction tools accurately calculate resistance, capacitance, and inductance parasitics in the most complex and advanced process node IC designs

Designing ICs for leading-edge process technology nodes is a challenging task that requires advanced tools and techniques to balance accuracy and productivity. The Calibre xACT and Calibre xACT 3D tools provide rule-based and field solver-based parasitic resistance and capacitance extraction, while the Calibre xL tool provides parasitic inductance extraction. Together, the Calibre PEX toolsuite provides the broad range of PEX techniques needed to accurately calculate parasitics in today’s complex advanced node IC designs, including finFET and GAAFET transistors.

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