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Technical Paper

Detecting and debugging soft check connectivity errors

Screenshot of IC layout showing highlighted soft check error.
An integrated circuit (IC) design will not work properly if power and ground nets are not strongly connected to the devices through the metal layers. Soft checks are a specific type of electrical rules check (ERC) that examine connectivity from the diffusion layers to the well (substrate) regions, and find any conflicts in the connections (nets) to be applied to the well regions. Understanding the attributes of well layer connectivity and how it is defined enables designers to develop a consistent approach to soft check debugging, which reduces debug time, improving efficiency and productivity. Accurate reporting, debugging, and correction of these connectivity errors helps ensure that a design will perform as intended when manufactured, enabling design companies to achieve their performance and reliability targets and market timelines for their products.

Designers use soft checks to find and debug well layer connectivity errors in layouts

Soft checks are a useful technique for finding and resolving soft connectivity issues between diffusion layers and well (substrate) regions of an IC design layout. Soft checks are run as part of the layout vs. schematic (LVS) layout extraction flow. Using soft checks in an LVS run helps designers ensure that the power and ground nets are not connecting through the well layers. Tools such as the Calibre RVE results viewer provide reporting and visualization functionality that help design teams establish consistent soft check debug flows across design styles and process nodes, with Calibre confidence in the results.

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