Signal integrity analysis for advanced process nodes and foundry device models requires precise characterization, which, in turn, requires an accurate extracted netlist. Designers must account for new and expanded impacts on parasitic extraction such as multi-patterning layouts, finFET devices, and changing resistance and capacitance models. The Calibre xACT platform supports advanced foundry device models and leading-edge process nodes with attofarad-accurate, deterministic, and repeatable results. Calibre xACT parasitic extraction provides the performance and capacity needed to handle multi-million instance digital designs, while its automatic optimization makes it the most versatile extraction tool available for digital, custom, analog, memory, MEMs and silicon photonics applications.
Signal integrity (SI) analysis must address multiple challenges, including high current, IR drop issues, and crosstalk noise. To provide accurate data for post-layout simulations and SI analysis, designers perform parasitic extraction and generate a netlist appending the parasitic resistance and capacitance to designed devices such as transistors. However, at each new process node, and for each new or enhanced device model or IC design style, designers must accurately measure new and magnified parasitic effects that can affect the performance, manufacturability, and power consumption of their IC designs. The Calibre xACT parasitic extraction tool provides the extraction accuracy and flexible capabilities designers require to help identify and resolve signal integrity concerns accurately and efficiently across all process nodes and IC design styles, including digital, analog, memory, MEMs, and silicon photonics, ensuring these designs reach production in a timely and profitable manner.