Early IC power management with automated design-stage layout optimization
Power is a key requirement in every IC design. Layout optimizations such as via and parallel run length insertions can help design teams achieve power management targets by reducing electromigration (EM) and voltage (IR) drop issues. However, P&R layout modification functionality is limited, and not guaranteed to be DRC-clean at signoff, while manual adjustments to custom/analog designs are tedious and time-consuming.
The Calibre DesignEnhancer tool offers design teams automated, analysis-based, design-stage layout enhancement with Calibre-clean results. Not only can designers reduce EM and IR drop issues in significantly less time, but they can also prepare designs for physical verification faster, further reducing time to tapeout. Multiple use models provide a range of options to meet design needs, while the push-button usability provides a high-level functionality that shields designers from low-level operational details and tasks. As part of the Calibre nmPlatform, the Calibre DesignEnhancer tool seamlessly integrates with all major IC design and P&R tools, and offers unparalleled runtime performance. This ease of use combined with fast runtimes offers P&R and custom/analog design teams a fast, integrated environment for implementing design modifications to reduce IR drop and EM and prepare for physical verification, while ensuring Calibre quality and confidence in the results.