Accelerate design verification with Calibre nmLVS Recon Compare

Layout versus schematic (LVS) comparison is a fundamental step in IC design verification, ensuring the functionality and reliability of integrated circuits (ICs). It involves verifying that the physical layout of the circuit matches its schematic representation, ensuring correctness and functionality. Traditionally, designers perform LVS comparison during signoff verification using dedicated tools that compare layout and schematic data, identifying any inconsistencies or errors. However, finding errors at the signoff stage leads to time-consuming iterations that delay design closure and time to market. While performing LVS earlier in the design flow would be better in many ways, early LVS comparison can generate millions of error results, many of which are due just to the incomplete status of the design.

The solution is the Calibre nmLVS™ Recon Compare solution, which delivers an intelligent shift-left process for fast and precise LVS comparison earlier in the design cycle. Calibre nmLVS Recon Compare enables early-stage LVS comparison by automating the black boxing of incomplete blocks and facilitating automatic port mapping. Designers can leverage innovative options for data partitioning, data re-use, task distribution and error management that can help them achieve faster LVS iterations on early-stage designs.

What you’ll learn:

• The purpose and importance of LVS comparison
• What challenges IC designers and verification engineers face in LVS comparison
• The benefits of taking a shift-left strategy for performing LVS comparison early in the design process using Calibre nmLVS Recon Compare
• Features of Calibre nmLVS Recon Compare and how it can result in quicker iterations and efficient debugging