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Technical Paper

A better way to estimate breakdown voltage for ESD design windows

Schematic view of devices on an electrical path between two given pins VDD2 and VSS, showing the path with the lowest total breakdown voltage
To ensure sufficient protection of integrated circuit (IC) design circuitry during an electrostatic discharge (ESD) event, IC chip designers must verify that ESD protection devices are properly implemented, and ESD discharge paths are efficient and robust. An ESD design window defines the voltage and current limits within which an ESD protection device operates during an ESD event. After selecting the type and size of an ESD protection device, designers know the operating and failing voltages and electrical current limits of the ESD protection device, but they must estimate the right-side boundary of the ESD design window, which is limited by the breakdown voltage of the victim circuitry. Using the Calibre PERC platform flow, designers can quickly and accurately identify the electrical path between two given pins with the lowest total breakdown voltage, which can be used to accurately estimate the upper voltage limit of an ESD design window, ensuring adequate ESD protection for IC design circuitry.

Accurately estimating upper breakdown voltage limits for ESD design windows ensures ESD protection devices adequately protect IC design circuitry against electrostatic discharge events

Meeting ESD design protection requirements is a critical part of today’s IC chip designs. The need to properly determine the upper voltage limit of an ESD design window exists in every scenario where an ESD protection device is used, but accurate estimates can be challenging. Using the breakdown voltage of the victim circuitry may be overly pessimistic, but overestimating the breakdown voltage may result in the victim circuitry being damaged before the ESD protection device fails or breaks down. The Calibre PERC reliability verification platform can automatically analyze a netlist and determine the lowest total breakdown voltage between any two given pins, enabling IC chip designers to more accurately estimate the best upper voltage limit for an ESD design window.

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