This fact sheet describes the 2.13 release of Xpedition IC packaging, which allows users to leverage custom user layers to create mechanical items for early analysis, import conductive plan shapes to support planning tradeoffs and better electrical analysis accuracy, use smart regions to enable rapid hierarchical device prototyping of complex ASICs and chiplets, re-use complex via array structures across designs, improve authoring/editing performance on large designs to reduce the number of cycles, and improve manufacturability and electrical signal behavior with teardrops on pads at route T-junctions.
