Veloce Coverage and Assertion App
Ensure verification quality and testbench completeness to achieve first-pass silicon success
The Veloce Coverage and Assertion App is a highly configurable verification toolset that focuses on ensuring every aspect of a design undergoes proper testing during the verification process. By providing detailed analysis and assertion-based debug techniques, the app supplies in-depth information regarding the coverage closure of testing in the form of a Unified Coverage Database (UCDB). The app supports Verilog and VHDL for coverage, SVA for assertions, and virtual and ICE mode usage. All this is done with minimal impact on performance, as coverage is run at emulation and prototyping speeds, with seamless integration for Siemens EDA coverage analysis tools and closure flows, such as Visualizer and Coverage Analyzer.
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