Veloce Visualizer App

According to 2022 Wilson research, design and verification engineers spend 46% of the project time debugging. Visualizer is the state-of-the-art debug platform suitable for today's functional verification challenges that are exponentially large and complex due to the presence of safety requirements, security requirements, hardware/software interactions, and complex system level integration. With the seamless merging of all the advanced debug features, and integration of UVM testbenches and Veloce emulation, Visualizer delivers a high performance debug for block level IP or full chip SoCs. Visualizer is built using latest technologies and is best suited to address the challenges of the future such as power streaming and analysis, code coverage Veloce Codelink SW debug, and protocol aware debug.

Key Benefits/Features include:

- Common debug solution for all HAV platforms such as Veloce Strato, Veloce Primo, and Veloce proFPGA, and simulation

- Very fast, high capacity, and scalable to support large to very large designs.

- One debug engine for all debug needs RTL debug, GLE designs debug, testbench debug, SW debug, assertion, transactions, power analysis, and functional coverage.

- Visualizer's feature richness, intuitive windows, and rich color set make debug easy, reduce time and improve productivity.