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fact sheet

UVM Verification IP

Integration verification tool for Tessent Embedded Analytics IP

The Tessent Embedded Analytics universal verification methodology (UVM) verification IP is a test environment based on the industry standard UVM. It contains sequence libraries and integration tests to help development teams carry out system-level verification of the Tessent Embedded Analytics IP deployed within an SoC. UVM VIP is a set of software classes and methods that reside within the test bench and is typically used during system-level simulation.

The UVM Verification IP shortens verification time and reduces development costs by verifying the integration of Embedded Analytics components with each other and into the SoC.