Tessent DefectSim
Testing Analog/Mixed-Signal Circuits
Tessent DefectSim injects a random selection of realistic defects into an AMS circuit, efficiently simulates multiple testbenches, and analyzes the results.
Related resources
Data integrity checks save time and resources in parallel IC design flows
Automated data integrity checks ensure quick, accurate identification and resolution of data mismatches in parallel IC design flows before physical verification, eliminating costly rework and schedule delays.
Custom integrity checks find early IC design implementation errors
Early-stage mistakes and out-of-sync data can limit a design team’s productivity. Technology-agnostic design integrity checks enable designers to find and fix gross and systemic issues before initiating downstream applications.
Finding systemic issues before SoC integration speeds time to tapeout
Early detection of systemic design issues like power to ground and bridge shorts enables designers to fix them before SoC integration and full-chip physical verification. The Calibre FDI utilities provide fast, automated checking.