fact sheet

Tessent UDAgent

Python-driven interface to the Embedded Analytics infrastructure

Tessent Embedded Analytics UDAgent architecture illustration

Tessent UDAgent is a software layer that connects to the Tessent Embedded Analytics infrastructure to facilitate communication between on-chip analytics modules and application software running external to the chip. It provides valuable services to interfacing software, including run-control of the target CPU and configuration and management of the Embedded Analytics infrastructure.

Tessent UDAgent is an integral part of the Embedded Analytics software toolchain. It is supplied as a bundled component of the Tessent SystemInsight integrated development environment, or as a standalone version.

High-level scripting interface to the Tessent Embedded Analytics infrastructure

Hardware, firmware, and software teams need an efficient, easy-to-use interfacing tool that gives control and oversight of the operation of hardware and software within an SoC.
In a complex, heterogeneous system developers need:

  • Flexible multi-core run control and trace
  • Configuration of Tessent on-chip analytics IP

Rapid and scalable roll-out to many host machines
UDAgent delivers these capabilities and more.

Used in conjunction with the customer’s preferred user interface, it provides an integrated view that encompasses real-time, protocol-aware monitoring of hardware structures within the SoC (including custom logic), single step and breakpoint code execution status for multiple processors (which may be based on different architectures), and instruction trace for many common CPU architectures. Key features include:

  • Utilize rich data generated by the Embedded Analytics on-chip monitoring infrastructure
  • Create an independent system-level monitoring, optimization and debug infrastructure
  • Gather and consolidate data from anywhere on the chip
  • Identify and analyze subtle bugs, including hardware-firmware-software interactions
  • Create sophisticated cross-triggering, breakpoint and control schemes to analyze the chip’s behavior

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