The Tessent TestKompress Streaming Scan Network (SSN) technology enables a true bottom-up design
flow that decouples core level and chip level DFT configuration. With SSN, it is no longer necessary to iterate between core level and chip level DFT configuration to achieve an optimal and cost-effective DFT configuration. Each core can be designed with the most optimal compression configuration for that core. The core level scan channel configuration is now completely independent of the number of chip-level
pins available for scan test.

Which cores should be tested concurrently can be selected programmatically rather than during design, with no impact on chip level routing. Leveraging independent shift and capture, SSN will automatically manage the test bandwidth across the cores to minimize test time.