RISC-V Enhanced Trace Encoder
A complete trace solution for RISC-V processors
The need for RISC-V trace
Complex systems are prone to imperfect software behaviors. These imperfections may be due to several factors, for example, interactions with other processor cores or peripherals, tight timing budgets, poor implementation, or a combination of the above. The imperfections impact the real‑time behavior of the system. Software that is not designed to minimize these imperfections leads to avoidable costs, attributed to underutilized CPUs, heating, power consumption, post-deployment defects, crashes, and poor longevity of the systems.
Understanding software behavior can be challenging but is key to tackling the imperfections. Therefore, providing software developers visibility of program execution is vital. Processor trace capability enables the software engineer to view the behavior of a program in detail, instruction‑by‑instruction without disrupting the system.
Effficient trace for RISC-V specification
The Efficient Trace for RISC‑V specification specifies a minimum level of trace functionality. The Enhanced Trace Encoder satisfies the full requirements of the Efficient Trace specification, while including many additional features not typically found within implementations provided by CPU vendors or in the open-source community. The following list of features are few of the many features offered by the Tessent Enhanced Trace Encoder.