fact sheet
QuestaSim
Sophisticated SoC verification solution
The QuestaSim verification solution delivers on these requirements for complex SoC designs. QuestaSim achieves industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC. Meanwhile, its Questa Visualizer debug environment provides high-performance, high-capacity debugging for dramatic regression throughput improvements when running large test suites.
QuestaSim Benefits
Industry-leading high performance multi-language simulator
High-performance, high-capacity unified debug
Reference simulator for LRM compatibility
UVM, SystemVerilog, VHDL, SystemC, and mixed language support
Native compiled, single kernel simulator technology
Next generation Visualizer debug environment
Code coverage and functional coverage
SVA and PSL assertions
Intelligent coverage closure
Integrated verification management and analysis
Simulate in advanced optimization mode
Best-in-class power-aware verification technology
Profiling for hotspot analysis
C code debug
X-propagation dynamic simulation
Real number modeling
Common coverage database and flows