Questa Verification IP

Fastest Time to Verification Sign-off

Siemens EDA Questa® Verification IP (QVIP) integrates seamlessly into all advanced verification environments on any simulator. With a consistent and easy-to-use UVM architecture across all protocols, QVIP ensures maximum productivity and flexibility for the verification of block level, subsystem, and SoC designs. Today’s designs rely heavily on a growing variety of complex industry standard interface protocols. QVIP enables engineers to effectively deal with this complexity, improves quality, and reduces schedule time by building Siemens EDA, a part of Siemens Digital Industries Software, protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees engineers from spending time developing BFMs, verification components, or VIP, so they can focus on the unique and high-value aspects of their designs.

Large Portfolio of Protocols and Memory Models

QVIP supports a large library of industry standard protocol and memory interfaces and devices. It includes standard SystemVerilog UVM components using a consistent, common architecture that allows rapid deployment and sharing of multiple protocols and memory models within a verification team. Test plans, compliance tests, test sequences, and protocol coverage are all included as SystemVerilog and XML source code, allowing easy reuse, extension, and debug. All QVIP components include a comprehensive set of protocol checks, error injection, and debug capabilities.