fact sheet
PowerPro® Power Optimization
Reading time: 5 minutes
Each stage of RTL design requires different methods to identify power reduction opportunities. PowerPro’s use-case independent static power checks can get you started on power very early on in the RTL design cycle; even before simulation vectors are available. You can perform low-power checking from the earliest RTL implementations right up to RTL IP power signoff.
As your RTL evolves, PowerPro’s micro-architectural analysis identifies opportunities for logic restructuring that can lead to significantly reduced power. Functional redundancy analysis finds redundant toggles that waste power and helps RTL designers identify root-cause and fix them.