Oasys-RTL
Physical RTL synthesis
The Oasys-RTL™ physical RTL synthesis solution is a revolutionary advancement in the state-of-the-art synthesis technology. It addresses the limitations of traditional RTL synthesis tools that were designed decades ago.
Oasys-RTL has been architected to meet the needs of complex, advanced- node, high performance designs with the capacity to handle 100+ million gates and up to 10X shorter runtimes. OasysRTL integrates full chip-level physical synthesis, floorplanning, and optimization at a higher level to enable RTL designers to accurately identify and resolve timing, routability, and power issues early in the design cycle. OasysRTL’s patented “PlaceFirst” synthesis technology enables optimization at the RTL level and delivers the best quality of results (QoR).
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