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fact sheet

ModelSim DE - sophisticated FPGA verification

Native compiled, single kernel simulator technology

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ModelSim DE is supported on the 32/64-bit Windows 7, 8.1, 10 and Linux RHEL 6-, 7- and SLES 11-based platforms.
ModelSim® DE packs an unprecedented level of verification capabilities in a cost-effective HDL simulation solution. In addition to supporting standard HDLs, ModelSim DE increases design quality and debug productivity.

ModelSim DE SKS

ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window.

For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim DE delivers a powerful simulation solution ideally suited for the verification of small and medium sized FPGA designs; especially designs with complex, mission critical functionality.

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