Mastering physical planning and optimizing for heterogeneous chip integration

The complexity of integrating chiplets into an advanced packaging platform, which includes various components like interposers, package substrates, and PCBs, can make managing the diverse elements and ensuring their seamless operation a daunting task.

Traditional device technology co-optimization methods may not fully consider the overall system's performance and cost implications, limiting the optimization potential across silicon, packages, interposers, and PCBs. In addition, addressing design-for-test challenges in testing 2.5/3D packages, such as die-to-die interconnect testing and KGD tests reruns, requires meticulous planning.

The second stage of heterogeneous integration: Assembly floorplanning

In this eBook, the second of four in the series, we focus on the second stage in heterogeneous chip integration, physical planning and optimizing.

This stage consists of:

1. Package assembly floorplanning, device stacking, and connectivity optimization
2. Design-for-test optimization
3. Mechanical component co-design

Download the eBook to learn how our methodology, coupled with advanced design tools, enables system-level technology co-optimization (STCO) for power, performance, area, cost, and reliability across silicon, packages, interposers, and PCBs.