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Delivering 3D IC innovations faster

Researcher holds integrated circuit chip
One of the biggest semiconductor engineering challenges today is delivering best-in-class devices while dealing with the technology scaling and cost limitations of monolithic IC design processes. To overcome these challenges, more companies are turning to heterogeneous integration and the 3D stacking of ICs and specialized chiplets (implemented in different processes geometries) into 3D ICs. Chiplets are small ICs specifically designed and optimized for operation within a package in conjunction with other chiplets and full-sized ICs. In heterogeneous designs, chips and chiplets are stacked and interconnected with vertical wiring. Designers can also combine them with 3D memory stacks, such as high bandwidth memory, on a silicon interposer within the package of a device.

Learn how to engineer a smarter future faster by downloading this ebook.

3D IC heterogeneous systems require co-optimization and co-simulation

Companies wanting to lead the way in 3D heterogenous integrated design must adopt four enabling approaches:

  • Transition from design-based to systems-based optimization for consistent system representation throughout design

  • Expanding the supply chain and tool ecosystem requiring interoperability and openness

  • Balancing design resources across multiple domains with system co-optimization (STCO)

  • Globalization requires complete system focus and cohesiveness across engineering teams (silicon, packaging and PCB) around the world

Learn how to use the Siemens heterogeneous 3D IC solution to create designs that meet or exceed your PPA goals and improve the differentiation, profitability and time to market of your next market-leading project.

Siemens 3D IC workflows: packed with powerful capabilities

The Siemens 3D IC heterogeneous package workflow catapults you into the future of IC design today, with:

  • Heterogeneous planning and co-design using prototyping/planning and integration of 3D IC packages enable a full system perspective for STCO-based modeling and early prototyping

  • Ecosystem interoperability and openness with industry standards, supporting third-party tools, certified reference flows, process design kits (PDK) and assembly design kits (ADK)

  • Physical verification through industry-proven assembly-level 3D IC verification (DRC/LVS)

  • Multi-domain testing for 3D IC architectures with known coverage through standards for 3D IC multi-domain testing

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