ON resistance is reduced by more than 61% (Pch) 39% (Nch)
ROHM uses Siemens Tanner to deliver best-in-class dual MOSFET devices
ROHM designs and manufactures integrated circuits (ICs), semiconductors and other
electronic components. These components find a home in the dynamic and ever-growing
wireless, computer, automotive, industrial and consumer electronics markets.
- Kyoto, Japan
- Tanner EDA L-Edit
- Industry Sector:
- Electronics, Semiconductor devices
Delivering class-leading low ON resistance
Today’s industrial motor and base station applications often have a 24V input voltage. The MOSFETS used in these application must be able to withstand voltage fluctuations between 40V to 60V. In addition, in today’s market, MOSFETs are expected to deliver higher speed switching together with lower ON resistance to further improve the efficiency and miniaturization of motors. Against this backdrop, using the latest design methodologies and process technologies allowed ROHM to develop its best-in-class dual MOSFETs, ROHM’s QH8Mx5/SH8Mx5 Series, which reduces ON resistance by up to 61 percent and 39 percent in the P channel and N channel MOSFETs, respectively, compared with the competition’s ±40V products. The company used Siemens Tanner™ L-Edit to design the layout of this device.
L-Edit is a design environment that realizes the designer’s challenge
“Designers are taking on challenges every day to reduce power consumption, reduce size and weight, improve high-heat resistance, and shorten the time-to-market for products,” says Mr. Yutani, Power Devices Business Unit, Devices development Division. “Now, we are working to shorten the turn around time (TAT) at the development stage by automating the test elementary group (TEG). The TEG layout is used to generate the optimal pattern for evaluating and controlling the process as well as individual device.”
In the structural design of power devices, the dimensions and pitch are determined by device simulation; and then, in order to select the optimal structure, ROHM has created several hundred TEG layout patterns. Through a trial-and-error process, the optimal structure layout is selected. “We are currently conducting a test operation of automating layout in the TCL language that incorporates the accumulated knowledge of designers,” says Yutani.
“With this process, we are expecting an 80 percent reduction of TEG layout design time once this automation work has been completed. And once the test operation has been completed, we will sequentially expand this automation to other structures, further improving the TAT flow, and promote TCL script-based optimization and efficiency within our company.”
“Tanner L-Edit software supports multiple languages, including C/C++, TCL, and Python, and you can choose whether to execute them in a parametric cell or on the command line. Therefore, until the contents of the program are determined, the coordinates can be calculated by Excel, converted into an ASCII file with a TCL command and executed on the command line. Once the contents of the program are universal, you can then create a parametric cell and determine which parameter values remain on the layout cell. This makes it possible to choose the most effective method to deploy for your design,” says Mr. Sanda, Power Devices Business Unit, Devices Development Division.
In addition, Tanner L-Edit supports both Windows and Linux. This flexibility reduces the burden of managing the design environment.
Parametric cell in TCL code, its parameters and an example of the generated layout. Layers are described in TCL and parametrically generated to improve layout efficiency.
Layout validation is also a new approach
“DRC verification of layout is an essential task to ensure design and product quality, but in power discrete device products, various processes,” says Yutani. “Creating a rule file for each process and applying the correct rules is far too complicated and the workload required to prevent mistakes and simply confirming whether we are using the right rules set can be very troublesome.”
“To strengthen this verification process, we changed our mindset and introduced a different approach in our DRC process,” says Yutani. “In the layout of our product, cells and parts of the basic structure are instanced regularly based on the rule, so we decided to move detecting the overlap and separation of DRC patterns that are incorporated into the basic structural parts, rather than detecting the dimension based on specifying minimum value. As a result, it is no longer necessary to prepare a conventional rule file that describes the minimum value for each process and product, and it is now possible to apply rules uniformly to all process and products.
Thankfully, there have been no delays in launching our products to market due to undetected DRC violation, but we have spent a considerable amount of time creating, operating, verifying and confirming rules to prevent this. We have been able to conduct DRC verification in a short time with a simple flow, workload and verification times have been greatly shortened, and reliability has also been ensured. Layout verification efficiency has dramatically increased by changing our approach to DRC. As a result, our preparation and specification of rules has become much simpler.”
Tanner L-Edit not only manages information such as layers and technologies in ASCII files, but also manages it as one database together with layout data, so it is easy to manage the data that designers can access, and you can build a flexible environment where you can easily try out the new ideas that you have just noticed.
Example of changing the approach from detecting DRC by dimension to detecting by overlapping DRC layers. By alternately add the “DRC1” and “DRC2” boxes in each part, overlap and/or space between instanced parts are detected.
Satisfied with support from the user’s perspective
“We are extremely happy with the support from Siemens EDA,” says Yutani. “Siemens EDA conducts interviews on usage appropriately and provides support from the user’s point of view such as workshops. From these experiences, even if there is any trouble, we are relieved that we can get the optimal support if we consult with Siemens EDA. In addition, technical inquiries can be registered with the support center and shared among members in the group, enabling efficient information sharing. We plan to continue to use Tanner tools to build an even more efficient design environment, so we expect to continue to provide high-quality support and products as a good partner.”