Workflows for tackling heterogeneous integration of chiplets
For 2.5D/3D semiconductor packaging
This webinar will discuss and present the high-level workflows required to support the design, analysis, and verification of these chiplets in heterogeneously integrated system-in-package (SIP) type designs.
What you will learn:
We will start by looking at how heterogeneous packaging is disrupting traditional design methodology, compare the difference between homogenous and heterogeneous design flows, and then spend the bulk of the webinar looking at the detailed workflows including touching on design data management and ecosystem-related activities. These questions and topics with be addressed:
- What are the macro dynamics driving the semiconductor packaging industry
- What is a homogeneous design flow, what is a heterogeneous design flow, and their differences
- What workflows are required to effectively design a multi-chiplet heterogeneously integrated semiconductor package
- Current state of the Ecosystem that is focused on supporting chiplets based heterogeneous integration
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