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A method to automatically promote timing constraints from IP level to the Top level

Image of electronic circuit board with a central microchip surrounded by various smaller components, highlighted with blue lighting.

When dealing with bottom-up methodology integrating lower blocks and sub-systems into the SOC design, there is a need to take advantage of existing timing constraints that may accompany the IP-block or previous versions of a sub-system design. When it comes down to definition of timing constraints, in such instances the designer is faced with the challenge of promoting existing timing constraints to higher level blocks and eventual SOC.

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