Timing exceptions demystified

One of the biggest challenges in timing constraints is the usage of timing exceptions such as false and multi-cycle paths. Because the usage of these exceptions are not well understood by designers, it often results in silicon failures. Furthermore, some EDA vendors are also responsible for adding to the confusion by promoting the blind usage of exceptions in order to promote their products.

Unfortunately, timing exceptions are a necessary evil that tend to creep into every SDC file, intentionally or non-intentionally during multiple stages of the ASIC design flow. However, when understood and used properly can provide great benefit.

This paper attempts to explain the timing exceptions and their proper usage in the ASIC flow.