Tackling verification challenges for PCIe® Gen5

The QVIP solution for PCIe® Gen5 helped Anritsu in several areas during development. Connectivity tests performed using QVIP were at par with those tests that are typically done in the real testbed. In PCIe Gen5, signals are as fast as 32GT/s and signal integrity shows greater effect. Therefore, debugging training protocol by looking at waveforms in the testbed is almost impossible. Using QVIP, Anritsu could simulate and analyze training functionality, which improved development efficiency significantly.

Verification challenges of new PCIe Gen5 features

Protocol verification was done through assertions. For PCIe Gen5, verification with QVIP found 18 complex assertion errors. These assertions provided the error locations in the design code, which made debugging easier. Anritsu fixed these errors successfully. Figure 4 shows an assertion error that was reported when “Precoding ON Bit 1b” was detected in the LTSSM states other than the Recovery state.

The key features of PCIe Gen5 offer several advantages, they also pose many additional challenges for verification engineers.

This paper discusses the PCIe Gen5 features and their verification challenges. It also describes a case study conducted in collaboration with Anritsu on how to address these challenges using a strong verification IP solution.