Questa Visualizer adds coverage analysis to the platform

Questa Visualizer Debug is Siemens EDA’s high-performance, scalable, context-aware debugger supporting the complete logic verification flow including simulation, emulation, prototyping, testbench, low-power, and assertion analysis. Visualizer recently introduced new functionality for coverage support giving the user many ways to analyze and improve coverage closure with ease. This paper will highlight some of the benefits that these kinds of features will bring to the process.

Overview of visualizer coverage

Intuitive and easy to use, Visualizer improves debug productivity of today's complex SoCs and FPGAs. Visualizer recently introduced new functionality for coverage support giving the user many ways to analyze and improve coverage closure with ease. Starting with coverage gives you another way to diagnose problems.

Visualizer provides great improvement to the coverage data representation, taking advantage of its existing rich visualization capabilities. It is built with improved capacity and performance to handle the largest coverage models. The visualization tools in Visualizer display UCDB results for both code coverage and functional coverage. Now that you have everything in Visualizer, you can go from coverage into the full power of debug in a single environment.
Both designers and verification engineers can analyze and debug coverage issues with the help of design and waveform data available in Visualizer, all in one tool. This is only the first step in the overall requirements for coverage closure productivity.

The Visualizer Debug Environment provides two invocation modes for analyzing coverage results using the unified coverage database (UCDB) obtained from Questa simulation:

• Coverage View Mode
  • allows accessing all coverage analysis windows
• Coverage Debugging Mode
  • allows accessing all coverage analysis windows in addition to all debugging capabilities within Visualizer