Accelerating verification of computational storage designs using Avery NVMe Verification IP

Computational storage is an emerging paradigm that integrates processing capabilities directly within storage devices. This paper outlines how this approach addresses the limitations of traditional NVM Express® (NVMe) SSDs and the performance characteristics of the newly introduced compute and subsystem local memory (SLM) namespaces. The paper also focuses on the verification framework provided by Avery NVMe Verification IP to validate the interoperability and performance of computational storage solutions. We will see how by using common APIs, diversified access to commands, data structures, SLM ranges using UVM features like callbacks and analysis components along with exhaustive compliance test suites and efficient debug mechanisms makes our solution highly adaptable for various types of device-defined or vendor specific programs, while keeping the high-level stimulus similar. Additionally, we discuss virtual in-circuit simulation (VICS); a system-level co-simulation approach for validating computational storage.