The Veloce Vista Virtual Prototype

Software-based methodologies involving virtual prototyping help to prove designs earlier and incorporate hardware and software development. Modeling, simulating and visualizing hardware's functional behavior under real-world operating conditions are all phases of virtual prototyping development. These Functional Models combined create the Virtual prototype (VP).

The Veloce Vista environment provides a simple way to create TLM platforms for SystemC structural code and link graphical symbols of individual TLM models to create a customer’s own virtual platform. The Veloce Vista environment has also the ability to import external TLM models and add them to the Vista model library.

Veloce Vista also enables software to be developed, integrated and validated on a virtual representation of the hardware that has more benefits over prototyping boards

Key Benefits for Architectural Exploration:

• Early assessment for functional and performance behavior of the HW system
• Visibility of key Hardware registers and attributes
• Support for large TLM models/cores and platforms

Veloce Vista for Software Validation;

• Industry standard systemC TLM 2.0 Virtual prototype executable
• Validation of software against early virtual Hardware model
• Fast software execution speed
• Non-intrusive tracing, profiling, and SW coverage capability
• Intuitive Eclipse based software debug environment
• Large set of Embedded software analysis and debug capabilities

Veloce Vista environment offerings:

• User Interface (UI)
• Platform creation
• Pre-defined TLMs Library
• Creating TLM function models with timing and power attributes
• Native TLM 2.0 block diagram for platform assembly
• Software development
• SW/HW analysis
• Debugging capabilities