Speed up early design rule exploration & physical verification

Running sign-off DRC during early design iterations not only results in long runtimes, but also huge numbers of errors, many of which are irrelevant. The Calibre nmDRC Recon functionality runs a selective DRC subset that ensures sufficient coverage to detect valid and critical early design issues. Designers can “gray box” unfinished blocks, checking only their interface region to capture interface violations. Post-processing and waiving of output results facilitates faster debugging and optimized fixing. providing efficient, productive early-stage IC design verification.

Fast, efficient, productive IC layout design-stage physical verification

Ensuring that early design-stage IC design physical verification actually enhances IC design and verification productivity means giving engineers the ability to focus on those errors that are both valid and critical in early-stage designs. The Calibre nmDRC Recon functionality provides selective DRC of early-stage designs that focuses on real, relevant errors, ignoring rule checks that generate meaningless errors in early design stages. Expanding that functionality to include techniques such as gray boxing further helps designers concentrate on checking only those portions of the design ready for verification. Calibre Auto-Waivers functionality provides automated post-processing and waiving of output results to facilitate even faster debugging and optimized fixing.