PAVE360 BACKPLANE
Connect virtual, hybrid and mixed-fidelity digital twin. Use real world stimulus to extend your pre-silicon validation capability
PAVE360 BACKPLANE connects and synchronizes the PAVE360 components to build the target digital twin. It can connect multiple components, systems, networks, and tools as long as they are based on automotive standards, even those from 3rd party vendors. BACKPLANE enables the creation of system-of-system digital twin.
Verwandte Ressourcen
Harvard University: Effective SW/HW Co-Design of Specialized ML Accelerators Using Catapult HLS
Harvard sheds light on their agile algo-hw co-design & co-verification methodology powered by HLS. It led to an order of magnitude improvement in the design effort across 3 generations edge AI accelerator SoCs.
Stanford University: Edge ML Accelerator SoC Design Using Catapult HLS
Describes the design and verification of the systolic array-based DNN accelerator taped out by Stanford, the performance optimizations of the accelerator, and the integration of the accelerator into an SoC.
How NVIDIA Uses High-Level Synthesis Tools for AI Hardware Accelerator Research
With constant change in AI/ML workloads, NVIDIA leverages a High-Level Synthesis design methodology based off SystemC and libraries like MatchLib to maximizing code reuse & minimizing design verification effort