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Optimizing EUV OPC runtime and pattern fidelity in DRAM manufacturing using memory OPC flow

Close-up image of a semiconductor wafer showing an array of integrated circuits. This image illustrates the precision manufacturing of modern microelectronics used in computing and electronic devices.

DRAM manufacturing faces significant challenges with EUV lithography, particularly long Optical Proximity Correction (OPC) runtimes for high-density structures like capacitor arrays and bit-line periphery. This bottleneck prolongs design cycles and increases costs. This paper introduces an innovative memory-optimized OPC flow, including a Slit-Aware Memory OPC approach, specifically designed to drastically reduce computation time while maintaining superior pattern fidelity. By leveraging memory's repetitive nature and advanced computational techniques, this method optimizes EUV mask simulation and effectively mitigates EUV-specific effects like thru-slit and flare. Experimental results demonstrate over 85% runtime reduction, improved mask consistency and accurate compensation for slit effects, providing a robust and efficient foundation for future DRAM manufacturing.

This paper was delivered as an invited presentation at the 2025 SPIE Advanced Lithography conferences and published here:

Shu De Gong, Sheng Tse Chen, Chun Cheng Liao, Teng Yen Huang, Renyang Meng, Kiho Yang, Werner Gillijns, Hsin-jung Lin, Shou-yuan Ma, JenHsiang Tsai, Ling Chieh Lin, Ryan Chou, Andrew Burbine, Alex Pearson, Xima Zhang, "Optimizing EUV OPC runtime and pattern fidelity in DRAM manufacturing using memory OPC flow," Proc. SPIE 13427, Novel Patterning Technologies 2025, 134270Y (25 April 2025); https://doi.org/10.1117/12.3051007

What you’ll learn:

  • The critical challenges of long EUV OPC runtimes and EUV-specific effects (slit, flare) in high-density DRAM patterning.
  • How an innovative memory-optimized OPC flow significantly reduces computation time while maintaining high pattern fidelity.
  • Experimental results demonstrating over 85% runtime reduction and improved mask consistency for DRAM manufacturing.

Who should read this:

  • DRAM lithography engineers
  • OPC engineers
  • Process integration engineers
  • Semiconductor manufacturing managers
  • EUV technologists

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