Teknisk dokument

An artificial intelligence machine learning (AI/ML) approach with cross-technology node learning for multi-layer process defect predictions

Diagram showing a potential weak process corner for Vx-Mx short detection, using previous process data to highlight minimum spacing risks in layout.

This technical paper presents an artificial intelligence and machine learning (AI/ML) framework for defect prediction in advanced semiconductor manufacturing. Focusing on feature-based learning, the methodology effectively addresses challenges posed by complex multi-layer interactions and limited defect data in new technology nodes. The workflow leverages historical process learnings for cross-node and cross-layer analysis, enabling more accurate and comprehensive detection of systematic defects with fewer known examples. Root cause analysis, enabled by feature ranking techniques like SHAP, facilitates process improvement and rapid defect elimination. Real-world applications demonstrate predictive accuracy in single- and multi-layer scenarios, with validated results through failure analysis. The approach saves yield learning cycle time and improves design robustness, offering significant value for design houses pursuing advanced process nodes.

This paper was originally delivered as an invited paper at the 2024 SPIE Advanced Lithography + Patterning event. Jonathan Ho, Xiaoyuan Qi, Fan Jiang, Yuyang Sun, Le Hong, "An artificial intelligence machine learning (AI/ML) approach with cross-technology node learning for multi-layer process defect predictions," Proc. SPIE 12954, DTCO and Computational Patterning III, 129540F (10 April 2024); https://doi.org/10.1117/12.3011296

What you’ll learn:

  • How feature-based AI/ML improves defect prediction over traditional pattern matching
  • Key steps in building and validating an effective defect prediction workflow
  • Methods for root cause analysis using feature ranking
  • Real-world applications of multi-layer and cross-node defect detection
  • Approaches for integrating historical process learning to accelerate yield improvement

Who should read this:

  • Semiconductor process engineers
  • IC layout designers and design-for-manufacturability (DFM) teams
  • Yield management specialists
  • R&D managers for advanced node technology
  • Academics and researchers in electronic design automation

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