Veloce Hardware-Assisted Verification: Complete, Unified and Progressive

Today, hardware emulators and FPGA prototypes have become mandatory verification platforms to thoroughly debug and validate an SoC design. Emulators excel in hardware debug and hardware/ software integration with quick design iterations made possible by fast compilation times and thorough design debug. They also allow for performance and power analysis driven by real-world workloads. Veloce Strato+ is an excellent choice for these tasks.

FPGA prototypes stand out in speed of execution by trading off design visibility. Veloce Primo offers unique capabilities for this task. Joining the two in a unified flow that harnesses the strengths of each leads to a powerful verification environment ideal for conquering the challenges posed by state-of-the-art SoC designs in the AI/ML, 5G, and automotive industry segments. A tight integration between hardware emulation and FPGA prototypes lowers the cost-per-verification cycle, accelerates the time to identify verification issues, optimizes the utilization of both verification platforms, and, ultimately, boosts the return on investment.

Hardware-assisted verification

Four key markets are driving hardware-assisted verification technology. They encompass networking, communications (specifically 5G), computing and storage, and transportation (not only automotive but any type of transportation where autonomous driving is possible).

All four key markets share a common theme: Software performance defines semiconductor success. They also share the same challenges, specifically power and performance analysis very early in the design flow to verify that the design specifications are met.

When hardware dominated chip design, verification was used to confirm that the hardware’s functional specifications were met and ensured no hardware bugs compromised design behavior. Today, meeting hardware functional specs is just the first step. As important is to verify that the DUT’s power and performance conform with target requirements. This can only be achieved by executing real-world workloads, frameworks, and a broad range of market-specific benchmarks. Finally, thorough SoC in-system validation has become necessary before releasing the DUT to manufacturing.