The three witches: preventing glitch nightmares on CDC paths

As electronic design companies are investing more in automotive and safety-critical designs, there is a renewed focus on design reliability. Glitches on clock-domain-crossing (CDC) signals reduce reliability and lead to potential silicon failures. Previously, companies focused on preventing and catching glitches on data multiplexing CDC paths. However, after deploying Questa Signoff CDC on multiple projects, we found it is even more critical to verify glitches on three types of CDC paths: unsynchronized CDC paths, combinational CDC paths, and data multiplexing CDC paths (the Three Witches).

Advantages of a Formal-Based Glitch Detection Methodology

We explain the glitch problems in these three types of CDC paths. Then we summarize an automated formal-based glitch detection methodology. In order to handle much more complex designs with even longer run times, we fractionated the methodology into a much more flexible, hierarchical, multi-stage and multi-processing flow. We describe the stages of the flow and how to achieve parallel processing.

With this hierarchical, multi-stage and multi-processing flow, users can perform gate-level CDC and glitch analysis much more efficiently than before. By transforming the RTL directives and waivers to the gate level, the hard work already performed at the RTL is reused instead of repeated.

A multi-stage, gate-level CDC and glitch analysis methodology has many advantages:

High quality of results
A formal-based approach for glitch verification generates less noisy and much higher quality results (a few glitches per thousands of paths), hence significantly reduces debug and triage effort.

Easy to debug
Using expression analysis and formal methods, the tool can identify the exact paths contributing to a glitch scenario and can pinpoint the convergence point where potential glitches can be generated.

Ability to handle large SoCs
A hierarchical approach can be utilized to complete CDC and glitch analysis on IP blocks first. Then the IP blocks are represented as grey boxes for analysis at the top level.

Quick refinement
A multi-stage process for gate-level CDC and glitch analysis enables incremental refinements with much-improved turnaround time and eliminates failure within a single process.

Multi-processing
As glitch analysis can be performed on multiple servers concurrently, it enables much more efficient usage of servers and memory.