technický dokument
Improving the reliability and performance of RF ICs with advanced EDA technology
Topological checking of RF circuits ensures the correct type of circuit structures are used where required, and that appropriate connections are made with these structures. Automated checking of subtle layout-dependent errors in a layout implementation, such as device asymmetry and mismatches, missing dummy devices, common centroid inaccuracies, current orientation matching, etc., minimizes the effects of crosstalk, shallow trench isolation, well proximity effects, and more. Automated post-layout fill optimization ensures symmetric and consistent fill patterns.