High-Speed I/O Verification with Analog FastSPICE

Inter-chip communication over high-speed serial I/O (HSIO) channels is now the norm, with numerous standardized protocols, such as PCI Express, HyperTransport, DDR3/4, XDR, GigaBit Ethernet, etc. With multiple Gbps signal rates (e.g., 8 Gbps PCI Express v3.0 data rate per lane), recovered clock jitter limits overall system performance. At these rates, accurately verifying total jitter with all contributing physical effects and under all expected conditions is critical. This must include device noise, which is a major contributor to jitter in nanometer process nodes, and parasitics, which contribute to frequency-dependent channel attenuation.

A typical HSIO architecture is shown in Figure 1. In many such circuits, the serializer contains a re-timer, ensuring that the output data is multiplexed correctly to the output serial stream. Phase mismatch between the data (here determined by clk0 and clk180) results in deterministic jitter applied to the serial data stream. Total system jitter is the sum of this deterministic jitter and the random jitter associated with device and system noise. The key circuits that impact output jitter include Phase-Locked Loop (PLL), Clock Data Recovery (CDR), Equalizer, and any other custom block in the signal path.