technický dokument

Can AI help manage the data needed for SoC verification?

Lauro Rizzatti interviews Thomas Delay, director of technical marketing in the Emulator Division at Siemens EDA, where they discuss whether AI can manage data for SoC verification

In Veloce Strato we create environments that take the data and analyze it for a specific purpose. The next step is to expand this capability and ease the pain of verification of large designs with large amounts of data at the full-system level.
This chart estimates storage capacity requirements per chip versus process node for an RTL-to-GDSII flow. (Source: Dell EMC)

Users are asking us to build in pointers and information on what is happening in the design so they can go back and find it based on what they know and what they know to look for. And then because they know where to look, they know which design team they should work with to resolve it. Sometimes the verification problem is simply a matter of not knowing where look or which designer team should be consulted. Maybe the sequence is incorrect or maybe some code loading is incorrect or maybe something else. What and where to look first in my 10-billion gate design? That’s the first problem.

Next, they’re looking for some help as to what data can be provided that would help them focus on one specific issue. We don’t need to tell them what the problem is. Of course, that would be even better. When we could provide narrowly focused data based on all the data collected, it would make the correlation between the various logs provided easier.

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