Analog FastSpice Platform: Enabling Nanometer Circuit Verification

Driven by consumer demand for cheaper, faster, and better, the semiconductor industry is continually pushing the migration to smaller process geometries to address performance, size, and cost.

This continued scaling of complex designs into the 16nm technology node and below is critical for applications ranging from high-performance computing to low-power mobile devices. For the 16nm technology node, the emergence and use of the FinFET 3D transistor, as compared to planar technology, brings many new opportunities to design, but it also introduces new challenges to design verification.

FinFET transistor technology addresses the performance versus power tradeoff consideration. Designers can run the transistors faster and use the same amount of power, as compared to the planar equivalent, or run them at the same performance using less power. This provides design teams the ability to balance performance and power to match the needs of each application.

As with many previous process geometry migrations, introduction of new design complexities will place increased pressure on getting the product out on time. While there are many benefits, such as, lower power and higher performance, without considering the impact on the design verification technology, these benefits could be easily negated if circuit simulation technology cannot keep up with these new challenges, causing design schedules to slip and therefore missing the market window.