video

Equivalence Checking for FPGA

Featuring OneSpin 360 EC-FPGA

Odhadovaná doba sledování: 20 min.

Functional correctness of FPGA synthesis from RTL code to final netlist

Systematic design errors introduced by synthesis or automated design refinement tools, or Trojan logic inserted by malicious actors, can be hard to detect and damaging if they make it into the final device. Using formal equivalence checking technology that has been used for ASIC design flows for many years, FPGA engineers can now exhaustively verify critical system components in their register transfer level (RTL) code to synthesized netlists and the final placed-and-routed FPGA designs, using an automated flow that is tightly integrated into the FPGA vendors’ platforms.

The Equivalence Checking for FPGA on-demand recording session will:

outline the differences between formal verification and simulation in the context of equivalence checking
define the verification challenges for sequential optimizations
discuss the advantages of a step netlist verification approach and related applications
present further related tasks that can be targeted using an equivalence checking verification flow

What You Will Learn:

The need of equivalence checking for FPGAs
Methodologies to apply equivalence checking
The advantages and challenges of stepwise netlist verification

Who Should Attend:

Design & Verification Engineers & Managers

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Learn how 360 EC-FPGA Enables Advanced FPGA Optimizations

A major benefit of the 360 EC-FPGA is to ensure that advanced FPGA synthesis optimizations, used to achieve competitive functionality, performance, power consumption, and cost targets, do not introduce functional errors. It supports all sequential synthesis optimizations performed in FPGA design flows. It verifies whole-chip, flat netlists, allowing for the most aggressive optimizations to be leveraged. 360 EC-FPGA verifies the optimized design 'as is' without gate-level simulation, design modifications or design restrictions, such as disabling synthesis optimizations. It eliminates the need for extensive scripting and many 'side files' generated by synthesis tools, providing a greater level of independence from the synthesis process. The tool is “self-starting” by providing automated setup capabilities that detect mapping information, clocks and resets, and other initialization settings. An advanced debugger is also included, which displays mismatches both directly in source and schematic windows, as well as through generated waveform traces.