Ease and secure the work with Voltage depended DRC rules by Calibre PERC Packaged check – Generate Voltage Text

In Foundry CMOS PDKs we observe an increasing number of voltage depended DRC rules the smaller the node gets. From a few rules in 65nm up to a three-digit number in Fin-Fet nodes. Typically the Foundry DRC uses built-in heuristics to calculate the voltage of a net, which provides a good starting point, but faces limitations in mixed voltage designs.

To obtain correct DRC results in mixed voltages designs, the designer needs to assign a proper voltage value on each affected layout net individually. This is difficult and error-prone, if the assignment is done manually and the challenge even increases with design size and hierarchy.

The Calibre PERC Packaged Check automates the net voltage assignment and helps designers to overcome the burden of manual work. Designers need to assign voltages only to a few nets, because Calibre PERC propagates voltages along paths and furthermore it checks voltage assignment for correctness.

In the presentation we show the methodology Infineon developed together with Siemens to work with voltage depended DRC rules, which is based on the Calibre PERC Packaged check – Generate Voltage Text