Addressing IR drop issues with analysis-driven, DRC-aware via insertion

Meeting IR drop targets is more and more difficult, driven by increases in power density and the resistivity of interconnects at deeper technology nodes. Correct-by-construction power grid design can result in conservative power grid layouts that severely limit the availability of routing tracks, impacting timely design closure.

One solution is to design a power grid that is “good enough” for most design scenarios, then use IR drop analysis to find hotspots where the power-grid must be enhanced with additional power straps and vias that are both DRC- and connectivity-clean. While place and route tools do an adequate job of inserting DRC-clean power straps, via insertion that meets all design rules is more challenging, given the limited technology files these tools use. Augmenting power connectivity at the boundary of IPs (e.g., memory) is another challenge for P&R tools.

The Calibre DesignEnhancer Via use model accesses Calibre sign-off DRC engines and connectivity, and has a full view of the design (including IP), providing a superior via insertion solution that ensures additional vias are DRC- and connectivity-clean. Calibre DesignEnhancer technology also enables designers to output layout modifications to both an incremental DEF file and an OASIS file. The incremental DEF file is used to automatically back-annotate the changes into the P&R database to enable sign-off IR drop analysis to verify the results.