Improve circuit performance and reliability with automated static check verification

Designers use a variety of techniques to combat electrical effects such as the growing dominance of parasitic resistance and capacitance, and increases in off-state leakage, while still achieving the desired power and performance. Such techniques include using different metals for local vs. global routing, implementing special circuit design techniques such as clock and power gating, adding multiple clock and power domains, using different circuit topologies, etc. However, the growing complexity of both ICs and their design techniques creates new challenges for IC verification flows and EDA verification tools.

In particular, checks that use manual techniques or dynamic simulations with SPICE are cumbersome, time-consuming, and no longer sufficient to guarantee full coverage in some cases. Calibre® PERC™ automated static check verification can help designers ensure that not only are their designs robust against electrical failure, and will perform as expected, but also that they can be delivered on time.