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Questa Reset Domain Crossing (RDC) Verification

Automated solutions that target RDC verification challenges

Using only your RTL as input, Questa RDC uses formal methods to statically and exhaustively identify reset domain crossing issues.
Designers increasingly use complex reset signaling architectures to meet highperformance, low-latency, and low-power requirements. The increase in reset signaling complexity, along with the emergence of multiple reset signaling networks in devices, is creating new verification challenges that cannot be addressed by RTL simulation. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains, and security domains or functionality.

Reset domain crossings require sophisticated, exhaustive analysis

The asynchronous reset domain crossings (RDC) that arise create metastability and signal reconvergence issues in the reset signaling networks — similar to the failures seen in asynchronous clock-domain crossings (CDC). Just as with CDC phenomena, the metastability induced by these asynchronous RDCs cannot be modeled or exhaustively covered by digital simulation, leaving designers open to the considerable risk of unpredictable chip behavior when samples come back from the fab, or worse, when in the field.

Automated, easy-to-use RDC verification

Questa RDC identifies reset domains, the related clock domains, and reset domain synchronizers, as well as low power structures via the Unified Power Format (UPF). The technology then exhaustively checks for any potential RDC errors, statically verifying that all signals crossing asynchronous reset and clock domain boundaries are guarded by RDC synchronizers. Any discovered issues are illustrated using familiar schematic and waveform displays.

Industry-leading scalability and quality of results

When analyzing billion gate designs, minimizing “noise” is critical; i.e., how many issues does the CDC analysis detect, and are these issues real or false positives. Questa CDC’s comprehensive, hierarchical, formal-based analysis searches through DUT elements for high throughput and noise minimization, simultaneously providing nd clock groupings are automatically inferred and reported with each run to confirm there are no unexpected changes. Questa RDC pinpoints all potential RDC issues and automatically identifies any existing RDC synchronization structures. No testbench is required.

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